Formal Verification Signoff Services

Amalent is a world-class formal verification semiconductor engineering services firm. Drawing on decades of deep experience in formal verification, our engineers will empower your team to deliver semiconductor designs with the maximum possible quality in the shortest amount of time.

What is FV Signoff?

Formal verification (FV) signoff uses exhaustive formal analysis to deliver end-to-end functional verification closure for digital logic designs. FV signoff is fundamentally different from traditional formal Assertion-Based Verification (ABV), which is a bug-hunting strategy. While ABV methods are useful, they don't deliver the verification maturity required for signoff.

The ABV approach is to sprinkle assertions throughout a design in an attempt to cover all the internal design structures and anticipate all the ways that they might fail. In contrast, Amalent's FV signoff uses end-to-end checkers, which inherently cover the entire design and expose all corner-case bugs.

Why Amalent?

With each generation, semiconductor designs get increasingly complex and harder to verify. With rising feature density and higher requirements for performance and security, FV signoff is a recognized critical need in the front-end design process. Yet highly skilled and experienced FV signoff engineers are in short supply.

Amalent's engineers have decades of combined experience in formal verification. We've helped scores of design teams across the industry to reap the benefits of FV signoff.

Past Projects

Amalent engineers have delivered formal signoff for a wide variety of simulation-resistant design blocks. These include the most complex modules of design architectures such as:

CPU (RISC-V and other ISAs)
ML / AI
GPU
Wireless communications
Networking
Network-on-Chip (NOC)
Bus Interface Controllers
Memory and Cache Controllers

Whatever your application domain, Amalent can help deliver first-pass silicon success.

Where to use FV Signoff

FV signoff can be used on almost any design, but it's most useful when you have new design blocks with a high degree of parallelism. Consider prioritizing new or recently modified blocks with lower verification maturity. FV signoff will quickly increase your confidence in newly minted code.

Consider also the factors that lead to a vast number of corner-case states, which are impossible to cover with stimulus-based verification approaches like simulation. A good candidate design is a block that must support a large number of distinct events at it's primary interfaces. The crossing of these events and all their possible temporal relationships create an enormous coverage space. When verifying these types of designs, FV signoff is the best tool for the job.

When to use FV Signoff

FV signoff can be deployed at any point in the design process with good results. However, for maximum benefit, we recommend applying FV signoff early in the design process to save time and effort in subsequent stages in the design flow. We will harden your design blocks before integration into IP level simulations and SoC level emulation, making those steps go more smoothly.

Contact information:

Email address:

contact@amalent.com

Mailing address:

15 Fitzgerald Rd suite 200

Ottawa, Ontario, Canada K2H 9G1

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